/***************************************************************************//**
* \file CapSense_ADC_Adc.h
* \version 3.0
*
* \brief
*   This file provides the sources of APIs specific to the ADC implementation.
*
* \see CapSense P4 v3.0 Datasheet
*
*//*****************************************************************************
* Copyright (2016), Cypress Semiconductor Corporation.
********************************************************************************
* This software is owned by Cypress Semiconductor Corporation (Cypress) and is
* protected by and subject to worldwide patent protection (United States and
* foreign), United States copyright laws and international treaty provisions.
* Cypress hereby grants to licensee a personal, non-exclusive, non-transferable
* license to copy, use, modify, create derivative works of, and compile the
* Cypress Source Code and derivative works for the sole purpose of creating
* custom software in support of licensee product to be used only in conjunction
* with a Cypress integrated circuit as specified in the applicable agreement.
* Any reproduction, modification, translation, compilation, or representation of
* this software except as specified above is prohibited without the express
* written permission of Cypress.
*
* Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
* REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
* Cypress reserves the right to make changes without further notice to the
* materials described herein. Cypress does not assume any liability arising out
* of the application or use of any product or circuit described herein. Cypress
* does not authorize its products for use as critical components in life-support
* systems where a malfunction or failure may reasonably be expected to result in
* significant injury to the user. The inclusion of Cypress' product in a life-
* support systems application implies that the manufacturer assumes all risk of
* such use and in doing so indemnifies Cypress against all charges. Use may be
* limited by and subject to the applicable Cypress software license agreement.
*******************************************************************************/

#if !defined(CY_CAPSENSE_CapSense_ADC_ADC_H)
#define CY_CAPSENSE_CapSense_ADC_ADC_H


#include "cytypes.h"
#include "CapSense_ADC_Structure.h"
#include "CapSense_ADC_Configuration.h"

#if (CapSense_ADC_ADC_EN)
    
/*******************************************************************************
* Function Prototypes 
*******************************************************************************/ 

/**
* \if SECTION_ADC_PUBLIC
* \addtogroup group_adc_public
* \{
*/

cystatus CapSense_ADC_AdcStartConvert(uint8 chId);
uint8 CapSense_ADC_AdcIsBusy(void);
uint16 CapSense_ADC_AdcReadResult_mVolts(uint8 chId);
uint16 CapSense_ADC_AdcGetResult_mVolts(uint8 chId);
cystatus CapSense_ADC_AdcCalibrate(void);
void CapSense_ADC_AdcStop(void);
void CapSense_ADC_AdcResume(void);


/** \}
* \endif */

CY_ISR_PROTO(CapSense_ADC_AdcIntrHandler);

/**
* \if SECTION_ADC_INTERNAL
* \addtogroup group_adc_internal
* \{
*/

void CapSense_ADC_AdcInitialize(void);
void CapSense_ADC_SetAdcChannel(uint8 chId, uint32 state);
void CapSense_ADC_ConfigAdcResources(void);
void CapSense_ADC_StartAdcFSM(uint32 measureMode);
cystatus CapSense_ADC_AdcCaptureResources(void);
cystatus CapSense_ADC_AdcReleaseResources(void);
void CapSense_ADC_ClearAdcChannels(void);

#define CapSense_ADC_AdcOFFSETNSIZE2MASK(o, s)  (((1uL << (s)) - 1uL) << (o))
/** \}
* \endif */

/**************************************
*           API Constants
**************************************/
    #define CapSense_ADC_AdcCHANNEL_0    (0U)
#if CapSense_ADC_ADC_TOTAL_CHANNELS > 1
    #define CapSense_ADC_AdcCHANNEL_1    (1U)
#if CapSense_ADC_ADC_TOTAL_CHANNELS > 2
    #define CapSense_ADC_AdcCHANNEL_2    (2U)
#if CapSense_ADC_ADC_TOTAL_CHANNELS > 3
    #define CapSense_ADC_AdcCHANNEL_3    (3U)
#if CapSense_ADC_ADC_TOTAL_CHANNELS > 4
    #define CapSense_ADC_AdcCHANNEL_4    (4U)
#if CapSense_ADC_ADC_TOTAL_CHANNELS > 5
    #define CapSense_ADC_AdcCHANNEL_5    (5U)
#if CapSense_ADC_ADC_TOTAL_CHANNELS > 6
    #define CapSense_ADC_AdcCHANNEL_6    (6U)
#if CapSense_ADC_ADC_TOTAL_CHANNELS > 7
    #define CapSense_ADC_AdcCHANNEL_7    (7U)
#if CapSense_ADC_ADC_TOTAL_CHANNELS > 8
    #define CapSense_ADC_AdcCHANNEL_8    (8U)
#if CapSense_ADC_ADC_TOTAL_CHANNELS > 9
    #define CapSense_ADC_AdcCHANNEL_9    (9U)
#endif
#endif
#endif
#endif
#endif
#endif
#endif
#endif
#endif

/* Error value if given bad channel ID. */
#define CapSense_ADC_AdcVALUE_BADCHANID       (0x0000FFFFUL)

/* Statuses defined for use with IsBusy */
#define CapSense_ADC_AdcSTATUS_LASTCHAN_MASK  (0x0000000FUL)
#define CapSense_ADC_AdcSTATUS_FSM_MASK       (0x000000F0UL)
#define CapSense_ADC_AdcSTATUS_IDLE           ( 0x00U)
#define CapSense_ADC_AdcSTATUS_CONVERTING     ( 0x10U)
#define CapSense_ADC_AdcSTATUS_CALIBPH1       ( 0x20U)
#define CapSense_ADC_AdcSTATUS_CALIBPH2       ( 0x40U)
#define CapSense_ADC_AdcSTATUS_OVERFLOW       ( 0x80U)

/* Potential channel states */
#define CapSense_ADC_AdcCHAN_CONNECT       (1UL)
#define CapSense_ADC_AdcCHAN_DISCONNECT    (0UL)

/* Input/Output constants */
#define CapSense_ADC_AdcHSIOM_PRTSEL_MASK     (0xFUL)
#define CapSense_ADC_AdcHSIOM_PRTSEL_GPIO     (0x0UL)
#define CapSense_ADC_AdcHSIOM_PRTSEL_AMUXBUSB (0x7UL)

#define CapSense_ADC_AdcGPIO_PC_MASK       (0x7UL)
#define CapSense_ADC_AdcGPIO_PC_DISCONNECT (0x0UL)
#define CapSense_ADC_AdcGPIO_PC_INPUT      (0x1UL)

/* Adc Config */
#define CapSense_ADC_AdcCONFIG_FILTER_DELAY_MASK    CapSense_ADC_AdcOFFSETNSIZE2MASK(\
                                                                       CYFLD_CSD_FILTER_DELAY__OFFSET, \
                                                                       CYFLD_CSD_FILTER_DELAY__SIZE)
#define CapSense_ADC_AdcCONFIG_SHIELD_DELAY_MASK    CapSense_ADC_AdcOFFSETNSIZE2MASK(\
                                                                       CYFLD_CSD_SHIELD_DELAY__OFFSET, \
                                                                       CYFLD_CSD_SHIELD_DELAY__SIZE)
#define CapSense_ADC_AdcCONFIG_SENSE_EN_MASK       CapSense_ADC_AdcOFFSETNSIZE2MASK(\
                                                                       CYFLD_CSD_SENSE_EN__OFFSET, \
                                                                       CYFLD_CSD_SENSE_EN__SIZE)
#define CapSense_ADC_AdcCONFIG_CHARGE_MODE_MASK     CapSense_ADC_AdcOFFSETNSIZE2MASK(\
                                                                       CYFLD_CSD_CHARGE_MODE__OFFSET, \
                                                                       CYFLD_CSD_CHARGE_MODE__SIZE)
#define CapSense_ADC_AdcCONFIG_MUTUAL_CAP_MASK     CapSense_ADC_AdcOFFSETNSIZE2MASK(\
                                                                       CYFLD_CSD_MUTUAL_CAP__OFFSET, \
                                                                       CYFLD_CSD_MUTUAL_CAP__SIZE)
#define CapSense_ADC_AdcCONFIG_CSX_DUAL_CNT_MASK    CapSense_ADC_AdcOFFSETNSIZE2MASK(\
                                                                       CYFLD_CSD_CSX_DUAL_CNT__OFFSET, \
                                                                       CYFLD_CSD_CSX_DUAL_CNT__SIZE)
#define CapSense_ADC_AdcCONFIG_DSI_COUNT_SEL_MASK    CapSense_ADC_AdcOFFSETNSIZE2MASK(\
                                                                       CYFLD_CSD_DSI_COUNT_SEL__OFFSET, \
                                                                       CYFLD_CSD_DSI_COUNT_SEL__SIZE)
#define CapSense_ADC_AdcCONFIG_DSI_SAMPLE_EN_MASK    CapSense_ADC_AdcOFFSETNSIZE2MASK(\
                                                                       CYFLD_CSD_DSI_SAMPLE_EN__OFFSET, \
                                                                       CYFLD_CSD_DSI_SAMPLE_EN__SIZE)
#define CapSense_ADC_AdcCONFIG_SAMPLE_SYNC_MASK    CapSense_ADC_AdcOFFSETNSIZE2MASK(\
                                                                       CYFLD_CSD_SAMPLE_SYNC__OFFSET, \
                                                                       CYFLD_CSD_SAMPLE_SYNC__SIZE)
#define CapSense_ADC_AdcCONFIG_DSI_SENSE_EN_MASK    CapSense_ADC_AdcOFFSETNSIZE2MASK(\
                                                                       CYFLD_CSD_DSI_SENSE_EN__OFFSET, \
                                                                       CYFLD_CSD_DSI_SENSE_EN__SIZE)
#define CapSense_ADC_AdcCONFIG_LP_MODE_MASK    CapSense_ADC_AdcOFFSETNSIZE2MASK(\
                                                                       CYFLD_CSD_LP_MODE__OFFSET, \
                                                                       CYFLD_CSD_LP_MODE__SIZE)
#define CapSense_ADC_AdcCONFIG_ENABLE_MASK    CapSense_ADC_AdcOFFSETNSIZE2MASK(\
                                                                       CYFLD_CSD_ENABLE__OFFSET, \
                                                                       CYFLD_CSD_ENABLE__SIZE)
#define CapSense_ADC_AdcCONFIG_DEFAULT        (CapSense_ADC_AdcCONFIG_ENABLE_MASK | \
                                                                 (2uL << CYFLD_CSD_FILTER_DELAY__OFFSET) | \
                                                                 CapSense_ADC_AdcCONFIG_SAMPLE_SYNC_MASK | \
                                                                 CapSense_ADC_AdcCONFIG_SENSE_EN_MASK | \
                                                                 CapSense_ADC_AdcCONFIG_DSI_COUNT_SEL_MASK)


/* Measurement modes */
#define CapSense_ADC_AdcMEASMODE_SHIFT    (CYFLD_CSD_ADC_MODE__OFFSET)
#define CapSense_ADC_AdcMEASMODE_MASK     (0x3UL << CapSense_ADC_AdcMEASMODE_SHIFT)
#define CapSense_ADC_AdcMEASMODE_OFF      (0x0UL << CapSense_ADC_AdcMEASMODE_SHIFT)
#define CapSense_ADC_AdcMEASMODE_VREF     (0x1UL << CapSense_ADC_AdcMEASMODE_SHIFT)
#define CapSense_ADC_AdcMEASMODE_VREFBY2  (0x2UL << CapSense_ADC_AdcMEASMODE_SHIFT)
#define CapSense_ADC_AdcMEASMODE_VIN      (0x3UL << CapSense_ADC_AdcMEASMODE_SHIFT)
#define CapSense_ADC_AdcMEASURE_APERTURE  (0x000000ffUL) /* 5us at 48 MHz */

/* SEQ_START field definitions */
#define CapSense_ADC_AdcFSMSETTING_START_SHIFT        (CYFLD_CSD_START__OFFSET)
#define CapSense_ADC_AdcFSMSETTING_START_MASK         (CapSense_ADC_AdcOFFSETNSIZE2MASK\
                          (CYFLD_CSD_START__OFFSET, CYFLD_CSD_START__SIZE))
#define CapSense_ADC_AdcFSMSETTING_STARTSEQ           (0x1UL << CapSense_ADC_AdcFSMSETTING_START_SHIFT)
#define CapSense_ADC_AdcFSMSETTING_SEQ_MODE_SHIFT     (CYFLD_CSD_SEQ_MODE__OFFSET)
#define CapSense_ADC_AdcFSMSETTING_SEQ_MODE_MASK      (CapSense_ADC_AdcOFFSETNSIZE2MASK\
                          (CYFLD_CSD_SEQ_MODE__OFFSET, CYFLD_CSD_SEQ_MODE__SIZE))
#define CapSense_ADC_AdcFSMSETTING_SEQ_MODE_ADC       (0x0UL)
#define CapSense_ADC_AdcFSMSETTING_SEQ_MODE_COARSE    (0x1UL << CapSense_ADC_AdcFSMSETTING_SEQ_MODE_SHIFT)
#define CapSense_ADC_AdcFSMSETTING_ABORT_SHIFT        (CYFLD_CSD_ABORT__OFFSET)
#define CapSense_ADC_AdcFSMSETTING_ABORT_MASK         (CapSense_ADC_AdcOFFSETNSIZE2MASK\
                          (CYFLD_CSD_ABORT__OFFSET, CYFLD_CSD_ABORT__SIZE))
#define CapSense_ADC_AdcFSMSETTING_ABORT              (0x1UL << CapSense_ADC_AdcFSMSETTING_ABORT_SHIFT)
#define CapSense_ADC_AdcFSMSETTING_DSI_START_EN_SHIFT (CYFLD_CSD_DSI_START_EN__OFFSET)
#define CapSense_ADC_AdcFSMSETTING_DSI_START_EN_MASK  (CapSense_ADC_AdcOFFSETNSIZE2MASK\
                          (CYFLD_CSD_DSI_START_EN__OFFSET, CYFLD_CSD_DSI_START_EN__SIZE))
#define CapSense_ADC_AdcFSMSETTING_DSI_START_EN       (0x1UL << CapSense_ADC_AdcFSMSETTING_DSI_START_EN_SHIFT)
#define CapSense_ADC_AdcFSMSETTING_AZ0SKIP_SHIFT      (CYFLD_CSD_AZ0_SKIP__OFFSET)
#define CapSense_ADC_AdcFSMSETTING_AZ0SKIP_MASK       (CapSense_ADC_AdcOFFSETNSIZE2MASK\
                          (CYFLD_CSD_AZ0_SKIP__OFFSET, CYFLD_CSD_AZ0_SKIP__SIZE))
#define CapSense_ADC_AdcFSMSETTING_AZ0SKIP            (0x1UL << CapSense_ADC_AdcFSMSETTING_AZ0SKIP_SHIFT)
#define CapSense_ADC_AdcFSMSETTING_AZ1SKIP_SHIFT      (CYFLD_CSD_AZ1_SKIP__OFFSET)
#define CapSense_ADC_AdcFSMSETTING_AZ1SKIP_MASK       (CapSense_ADC_AdcOFFSETNSIZE2MASK\
                          (CYFLD_CSD_AZ1_SKIP__OFFSET, CYFLD_CSD_AZ1_SKIP__SIZE))
#define CapSense_ADC_AdcFSMSETTING_AZ1SKIP            (0x1UL << CapSense_ADC_AdcFSMSETTING_AZ1SKIP_SHIFT)

#define CapSense_ADC_AdcFSMSETTING_AZ        (0x00000000UL)
#define CapSense_ADC_AdcFSMSETTING_AZSKIP    (CapSense_ADC_AdcFSMSETTING_AZ0SKIP | \
                                                                 CapSense_ADC_AdcFSMSETTING_AZ1SKIP)
#define CapSense_ADC_AdcFSMSETTING_DSIIGNORE (0x00000000UL)
#define CapSense_ADC_AdcFSMSETTING_NOABORT   (0x00000000UL)
#define CapSense_ADC_AdcFSMSETTING_SEQMODE   (0x00000000UL)
#define CapSense_ADC_AdcFSMSETTING_START     (0x00000001UL)

/* Interrupt definitions */
#define CapSense_ADC_AdcINTERRUPT_SHIFT       (CYFLD_CSD_ADC_RES__OFFSET)
#define CapSense_ADC_AdcINTERRUPT_MASK        (0x1UL << CapSense_ADC_AdcINTERRUPT_SHIFT)
#define CapSense_ADC_AdcINTERRUPT_CLEAR       (0x00000000UL)
#define CapSense_ADC_AdcINTERRUPT_SET         (CapSense_ADC_AdcINTERRUPT_MASK)

/* IDACB definitions */
/* The idac configuration for ADC use is mostly static, with only the VAL field
   varying. 
   Dynamic Polarity = 1 << 7
   Polarity (normal) = 0 << 8
   Balance, Leg1, Leg2 modes = don't care.
   DSI Control Enable (no mix) = 0 << 21
   Range (low) = 0 << 22
   Leg1, Leg2 enable = 0
   Leg3 enable = 1 << 26
   
   */
#define CapSense_ADC_AdcIDACB_CONFIG          (0x04000080UL)

/* Switch definitions */
#define CapSense_ADC_AdcSW_HSP_DEFAULT     (0x10000000UL)
#define CapSense_ADC_AdcSW_SHIELD_DEFAULT  (0x00000000UL)
#define CapSense_ADC_AdcSW_BYP_DEFAULT     (0x00110000UL)
#define CapSense_ADC_AdcSW_CMPP_DEFAULT    (0x00000000UL)
#define CapSense_ADC_AdcSW_CMPN_DEFAULT    (0x00000000UL)
#define CapSense_ADC_AdcSW_REFGEN_DEFAULT  (0x01000000UL)
#define CapSense_ADC_AdcSW_FWMOD_DEFAULT   (0x01100000UL)
#define CapSense_ADC_AdcSW_FWTANK_DEFAULT  (0x01100000UL)

#define CapSense_ADC_AdcSW_CTANK_PINSHIFT  (9uL)
#define CapSense_ADC_AdcSW_CMOD_PINSHIFT   (6uL)
#define CapSense_ADC_AdcSW_CMOD_PORT_MASK  (0x400uL)
#define CapSense_ADC_AdcSW_DSI_CMOD        (1uL << 4)
#define CapSense_ADC_AdcSW_DSI_CTANK       (1uL << 0)


#define CapSense_ADC_AdcVDDA_MV   ((CYDEV_VDDA_MV * 255UL) / 5500UL)
#define CapSense_ADC_AdcLVTHRESH  ((2700UL * 255UL) / 5500UL)
#define CapSense_ADC_AdcHVTHRESH  ((4800UL * 255UL) / 5500UL)

/* Vrefhi is achieved via a gain applied to a source. Source value is usually 1.2V */
#define CapSense_ADC_AdcVREFSRC_MV        (1200UL)


/* RefGen gain is 32 / Reg value + 1.  Solve for Reg value here using known input 
voltage Vref and desired output ovltage, VrefHi. By omitting the one from the
calculation, the Reg Value always results in an under-shoot of the target Vrefhi.
Vrefhi must be < VDD - 600mV. */
#define CapSense_ADC_AdcREFGEN_GAINTMP ((32UL * CapSense_ADC_AdcVREFSRC_MV) / CapSense_ADC_ADC_VREF_MV)

#define CapSense_ADC_AdcREFGEN_GAIN    ((CapSense_ADC_AdcREFGEN_GAINTMP < 32UL) ? CapSense_ADC_AdcREFGEN_GAINTMP : 31UL)
#define CapSense_ADC_AdcREFGEN_GAIN_SHIFT (CYFLD_CSD_GAIN__OFFSET)

/* Actual VREFHI is used in calculations. */
#define CapSense_ADC_AdcVREFHI_MV         ((CapSense_ADC_AdcVREFSRC_MV * 32UL) / (CapSense_ADC_AdcREFGEN_GAIN + 1UL))
/* At low voltage, REFGEN is enabled and bypassed. */
#define CapSense_ADC_AdcREFGEN_LV         (0x00000011UL)
#define CapSense_ADC_AdcSW_AMUBUF_LV      (0x01000100UL)
#define CapSense_ADC_AdcSW_HSN_LV         (0x00100000UL)
#define CapSense_ADC_AdcAMBUF_LV          (0x00000002UL)
#define CapSense_ADC_AdcREFGEN_NORM       (0x00000041UL | (CapSense_ADC_AdcREFGEN_GAIN << CapSense_ADC_AdcREFGEN_GAIN_SHIFT))
#define CapSense_ADC_AdcSW_AMUBUF_NORM    (0x00000000UL)
#define CapSense_ADC_AdcSW_HSN_NORM       (0x00100000UL)

/* Sense defines */
#define CapSense_ADC_AdcSENSE_SINGLEDIV (0x1ul)

/* HSCOMP definitions */
#define CapSense_ADC_AdcHSCMP_AZ_SHIFT    (31UL)
#define CapSense_ADC_AdcHSCMP_AZ_DEFAULT  (0x00000001UL | (CapSense_ADC_ADC_AZ_EN << CapSense_ADC_AdcHSCMP_AZ_SHIFT))

/* ADC_RES definitions */
#define CapSense_ADC_AdcADC_RES_OVERFLOW_MASK  (0x40000000UL)
#define CapSense_ADC_AdcADC_RES_HSCMPPOL_MASK  (0x00010000UL)
#define CapSense_ADC_AdcADC_RES_VALUE_MASK     (0x0000FFFFUL)
#define CapSense_ADC_AdcUNDERFLOW_LIMIT        (8000U)

/* Register definitions */
#define CapSense_ADC_AdcCONFIG_REG    (* ( reg32 *) CYREG_CSD_CONFIG )
#define CapSense_ADC_AdcSPARE_REG     (* ( reg32 *) CYREG_CSD_SPARE )
#define CapSense_ADC_AdcSTATUS_REG    (* ( reg32 *) CYREG_CSD_STATUS )
#define CapSense_ADC_AdcSTAT_SEQ_REG    (* ( reg32 *) CYREG_CSD_STAT_SEQ )
#define CapSense_ADC_AdcSTAT_CNTS_REG    (* ( reg32 *) CYREG_CSD_STAT_CNTS )
#define CapSense_ADC_AdcRESULT_VAL1_REG    (* ( reg32 *) CYREG_CSD_RESULT_VAL1 )
#define CapSense_ADC_AdcRESULT_VAL2_REG    (* ( reg32 *) CYREG_CSD_RESULT_VAL2 )
#define CapSense_ADC_AdcADC_RES_REG    (* ( reg32 *) CYREG_CSD_ADC_RES )
#define CapSense_ADC_AdcINTR_REG       (* ( reg32 *) CYREG_CSD_INTR )
#define CapSense_ADC_AdcINTR_SET_REG    (* ( reg32 *) CYREG_CSD_INTR_SET )
#define CapSense_ADC_AdcINTR_MASK_REG    (* ( reg32 *) CYREG_CSD_INTR_MASK )
#define CapSense_ADC_AdcINTR_MASKED_REG    (* ( reg32 *) CYREG_CSD_INTR_MASKED )
#define CapSense_ADC_AdcHSCMP_REG     (* ( reg32 *) CYREG_CSD_HSCMP )
#define CapSense_ADC_AdcAMBUF_REG     (* ( reg32 *) CYREG_CSD_AMBUF )
#define CapSense_ADC_AdcREFGEN_REG    (* ( reg32 *) CYREG_CSD_REFGEN )
#define CapSense_ADC_AdcCSDCMP_REG    (* ( reg32 *) CYREG_CSD_CSDCMP )
#define CapSense_ADC_AdcIDACA_REG     (* ( reg32 *) CYREG_CSD_IDACA )
#define CapSense_ADC_AdcIDACB_REG     (* ( reg32 *) CYREG_CSD_IDACB )
#define CapSense_ADC_AdcSW_RES_REG    (* ( reg32 *) CYREG_CSD_SW_RES )
#define CapSense_ADC_AdcSENSE_PERIOD_REG    (* ( reg32 *) CYREG_CSD_SENSE_PERIOD )
#define CapSense_ADC_AdcSENSE_DUTY_REG       (* ( reg32 *) CYREG_CSD_SENSE_DUTY )
#define CapSense_ADC_AdcSW_HS_P_SEL_REG      (* ( reg32 *) CYREG_CSD_SW_HS_P_SEL )
#define CapSense_ADC_AdcSW_HS_N_SEL_REG      (* ( reg32 *) CYREG_CSD_SW_HS_N_SEL )
#define CapSense_ADC_AdcSW_SHIELD_SEL_REG    (* ( reg32 *) CYREG_CSD_SW_SHIELD_SEL )
#define CapSense_ADC_AdcSW_AMUXBUF_SEL_REG    (* ( reg32 *) CYREG_CSD_SW_AMUXBUF_SEL )
#define CapSense_ADC_AdcSW_BYP_SEL_REG       (* ( reg32 *) CYREG_CSD_SW_BYP_SEL )
#define CapSense_ADC_AdcSW_CMP_P_SEL_REG    (* ( reg32 *) CYREG_CSD_SW_CMP_P_SEL )
#define CapSense_ADC_AdcSW_CMP_N_SEL_REG    (* ( reg32 *) CYREG_CSD_SW_CMP_N_SEL )
#define CapSense_ADC_AdcSW_REFGEN_SEL_REG    (* ( reg32 *) CYREG_CSD_SW_REFGEN_SEL )
#define CapSense_ADC_AdcSW_FW_MOD_SEL_REG    (* ( reg32 *) CYREG_CSD_SW_FW_MOD_SEL )
#define CapSense_ADC_AdcSW_FW_TANK_SEL_REG    (* ( reg32 *) CYREG_CSD_SW_FW_TANK_SEL )
#define CapSense_ADC_AdcSW_DSI_SEL_REG      (* ( reg32 *) CYREG_CSD_SW_DSI_SEL )
#define CapSense_ADC_AdcSEQ_TIME_REG        (* ( reg32 *) CYREG_CSD_SEQ_TIME )
#define CapSense_ADC_AdcSEQ_INIT_CNT_REG    (* ( reg32 *) CYREG_CSD_SEQ_INIT_CNT )
#define CapSense_ADC_AdcSEQ_NORM_CNT_REG    (* ( reg32 *) CYREG_CSD_SEQ_NORM_CNT )
#define CapSense_ADC_AdcADC_CTL_REG        (* ( reg32 *) CYREG_CSD_ADC_CTL )
#define CapSense_ADC_AdcSEQ_START_REG       (* ( reg32 *) CYREG_CSD_SEQ_START )
#define CapSense_ADC_AdcTRIM_CTRL_REG       (* ( reg32 *) CYREG_CSD_TRIM_CTRL )


#define CapSense_ADC_AdcCONFIG_PTR    ( ( reg32 *) CYREG_CSD_CONFIG )
#define CapSense_ADC_AdcSPARE_PTR     ( ( reg32 *) CYREG_CSD_SPARE )
#define CapSense_ADC_AdcSTATUS_PTR    ( ( reg32 *) CYREG_CSD_STATUS )
#define CapSense_ADC_AdcSTAT_SEQ_PTR    ( ( reg32 *) CYREG_CSD_STAT_SEQ )
#define CapSense_ADC_AdcSTAT_CNTS_PTR    ( ( reg32 *) CYREG_CSD_STAT_CNTS )
#define CapSense_ADC_AdcRESULT_VAL1_PTR    ( ( reg32 *) CYREG_CSD_RESULT_VAL1 )
#define CapSense_ADC_AdcRESULT_VAL2_PTR    ( ( reg32 *) CYREG_CSD_RESULT_VAL2 )
#define CapSense_ADC_AdcADC_RES_PTR    ( ( reg32 *) CYREG_CSD_ADC_RES )
#define CapSense_ADC_AdcINTR_PTR       ( ( reg32 *) CYREG_CSD_INTR )
#define CapSense_ADC_AdcINTR_SET_PTR    ( ( reg32 *) CYREG_CSD_INTR_SET )
#define CapSense_ADC_AdcINTR_MASK_PTR    ( ( reg32 *) CYREG_CSD_INTR_MASK )
#define CapSense_ADC_AdcINTR_MASKED_PTR    ( ( reg32 *) CYREG_CSD_INTR_MASKED )
#define CapSense_ADC_AdcHSCMP_PTR     ( ( reg32 *) CYREG_CSD_HSCMP )
#define CapSense_ADC_AdcAMBUF_PTR     ( ( reg32 *) CYREG_CSD_AMBUF )
#define CapSense_ADC_AdcREFGEN_PTR    ( ( reg32 *) CYREG_CSD_REFGEN )
#define CapSense_ADC_AdcCSDCMP_PTR    ( ( reg32 *) CYREG_CSD_CSDCMP )
#define CapSense_ADC_AdcIDACA_PTR     ( ( reg32 *) CYREG_CSD_IDACA )
#define CapSense_ADC_AdcIDACB_PTR     ( ( reg32 *) CYREG_CSD_IDACB )
#define CapSense_ADC_AdcSW_RES_PTR    ( ( reg32 *) CYREG_CSD_SW_RES )
#define CapSense_ADC_AdcSENSE_PERIOD_PTR    ( ( reg32 *) CYREG_CSD_SENSE_PERIOD )
#define CapSense_ADC_AdcSENSE_DUTY_PTR       ( ( reg32 *) CYREG_CSD_SENSE_DUTY )
#define CapSense_ADC_AdcSW_HS_P_SEL_PTR      ( ( reg32 *) CYREG_CSD_SW_HS_P_SEL )
#define CapSense_ADC_AdcSW_HS_N_SEL_PTR      ( ( reg32 *) CYREG_CSD_SW_HS_N_SEL )
#define CapSense_ADC_AdcSW_SHIELD_SEL_PTR    ( ( reg32 *) CYREG_CSD_SW_SHIELD_SEL )
#define CapSense_ADC_AdcSW_AMUXBUF_SEL_PTR    ( ( reg32 *) CYREG_CSD_SW_AMUXBUF_SEL )
#define CapSense_ADC_AdcSW_BYP_SEL_PTR       ( ( reg32 *) CYREG_CSD_SW_BYP_SEL )
#define CapSense_ADC_AdcSW_CMP_P_SEL_PTR    ( ( reg32 *) CYREG_CSD_SW_CMP_P_SEL )
#define CapSense_ADC_AdcSW_CMP_N_SEL_PTR    ( ( reg32 *) CYREG_CSD_SW_CMP_N_SEL )
#define CapSense_ADC_AdcSW_REFGEN_SEL_PTR    ( ( reg32 *) CYREG_CSD_SW_REFGEN_SEL )
#define CapSense_ADC_AdcSW_FW_MOD_SEL_PTR    ( ( reg32 *) CYREG_CSD_SW_FW_MOD_SEL )
#define CapSense_ADC_AdcSW_FW_TANK_SEL_PTR    ( ( reg32 *) CYREG_CSD_SW_FW_TANK_SEL )
#define CapSense_ADC_AdcSW_DSI_SEL_PTR      ( ( reg32 *) CYREG_CSD_SW_DSI_SEL )
#define CapSense_ADC_AdcSEQ_TIME_PTR        ( ( reg32 *) CYREG_CSD_SEQ_TIME )
#define CapSense_ADC_AdcSEQ_INIT_CNT_PTR    ( ( reg32 *) CYREG_CSD_SEQ_INIT_CNT )
#define CapSense_ADC_AdcSEQ_NORM_CNT_PTR    ( ( reg32 *) CYREG_CSD_SEQ_NORM_CNT )
#define CapSense_ADC_AdcADC_CTL_PTR        ( ( reg32 *) CYREG_CSD_ADC_CTL )
#define CapSense_ADC_AdcSEQ_START_PTR       ( ( reg32 *) CYREG_CSD_SEQ_START )
#define CapSense_ADC_AdcTRIM_CTRL_PTR       ( ( reg32 *) CYREG_CSD_TRIM_CTRL )


#endif 	/* CapSense_ADC_ADC_EN */

#endif	/* CY_CAPSENSE_CapSense_ADC_ADC_H */


/* [] END OF FILE */
